1. Field of the Invention
The present invention relates to a variable gain amplifier and a differential amplifier. Particularly, the present invention relates to a variable gain amplifier and a differential amplifier which comprise a signal amplifying transistor, and gain control transistors at output and non-output sides, whose current paths are respectively connected to the current path of the signal amplifying transistor.
2. Description of the Related Art
(Prior Art 1)
As a structure of a single-ended variable gain amplifier, for example, the one shown in FIG. 9 has conventionally been known. The transistors included in the structure shown in FIG. 9 may be MOS transistors in some cases. In the structure shown in FIG. 9, as the amount of a current flowing into the collector of the upper output transistor 4 changes, the amount of negative feedback to the signal amplifying transistor 3 changes. Particularly, when the amplification degree is the smallest, there arises a problem that almost no negative feedback returns.
FIG. 10 is a circuit diagram showing a structure of a differential amplifier comprising two of the variable gain amplifier circuit of the Prior Art 1.
FIG. 11A to FIG. 11D are graphs showing the results of simulations conducted on the differential amplifier shown in FIG. 10. Specifically, FIG. 11A shows a graph plotting the changes of noise figure (hereinafter referred to as NF) with respect to the changes of gain control voltage, regarding the cases where the frequency of an input signal input to the differential amplifier shown in FIG. 10 is 50 MHz, 275 MHz, and 500 MHz respectively. FIG. 11B shows a graph plotting the changes of S parameter S11 indicating an input reflection characteristic, with respect to the changes of gain control voltage, regarding the same cases as above. FIG. 11C shows a graph plotting the changes of S parameter S21 indicating an input transmission characteristic, with respect to he changes of gain control voltage, regarding the same cases. FIG. 11D shows a graph plotting the changes of third order input intercept point (hereinafter referred to as IIP3) indicating an intermodulation distortion characteristic, with respect to the changes of gain control voltage, regarding the same cases. In FIG. 11A to FIG. 11D, the plot of the case where the frequency of the input signal is 500 MHz is indicated by the boldest solid line, the plot of the case where the frequency of the input signal is 275 MHz is indicated by the next boldest solid line, and the plot of the case where the frequency of the input signal is 50 MHz is indicated by the thin solid line, respectively.
In the graphs shown in FIG. 11A to FIG. 11D, the value VAGC on the X axis indicates, in volt unit, a ½ value of the voltage at an application point 9 in the structure of FIG. 10, with respect to the electric potential at an application point 10 as a reference. The bases of transistors 4a and 4b are each connected to the application point 9, and the bases of transistors 5a and 5b are each connected to the application point 10. Gain fluctuations arising in accordance with the changes of the value VAGC are expressed by the changes of the value of S21 shown in FIG. 11C. The simulations on the value of IIP3 were conducted under a setting that two tone signals having frequencies distanced from each other by 20 kHz were input at an intensity of −50 dBm.
With reference to FIG. 11D, it is known that the results of the simulations under the settings that the frequency of the input signal is 275 MHz and 500 MHz are influenced by parasitic capacitance contained in the transistors. Accordingly, it can be considered that the simulation result of the case where the frequency of the input signal is 50 MHz is the closest to the result that can be achieved when ideal transistor elements are used.
According to these simulation results, a range of 60 dB or greater can be secured as the variable range of the gain of the differential amplifier shown in FIG. 10, in the case where the frequency of the input signal is 50 MHz. On the other hand, with reference to the plot (thin solid line) of the case where the frequency of the input signal is 50 MHz in FIG. 11D, it is known that when the gain is reduced, the amount of negative feedback is also reduced, which leads to the deterioration of IIP3. With reference to FIG. 11B, it is known that the values of S11 are −30 dB or lower when the gain is sufficiently large, while the values deteriorate to about −3 dB as the gain is reduced.
Wide-band variable gain amplifiers are generally required to be able to achieve values of S11, which are about −10 dB or lower over a wide band regardless of the gain, and to be able to cause no reduction of IIP3 even when the gain is reduced. According to the above-described simulation results, the differential amplifier according to the Prior Art 1 cannot satisfy these requirements.
(Prior Art 2)
As another structure conventionally known, for example, a structure shown in FIG. 12 is available. This structure corresponds to one that was published in the year 2003 as U.S. Pat. No. 6,600,371 B2.
The structure shown in FIG. 12 can constantly return a fixed amount of negative feedback even if the gain changes, thus can solve the problem of the above-described Prior Art 1. However, the structure of FIG. 12 has the following deficiencies.
(1) In the structure shown in FIG. 12, the gain variable range, i.e., the ratio of the maximum gain and the minimum gain is determined by the ratio of resistance values of resistors AP and BP, and the ratio of resistance values of resistors AM and BM. AP(BP) and AM(BM) have the same resistance in a balanced structure such as shown in FIG. 12. Hence, in the structure of FIG. 12, it is required to set the ratios of resistance values to 100:1 in order to obtain a gain variable range of, for example, 40 dB. However, in a case where the structure of FIG. 12 is realized by an integrated circuit, it is necessary to secure vast areas to be occupied by the resistors on the die to achieve ratios of resistance values of 100:1 exactly, when the same kind of sheet resistor is used for AP and BP. Accordingly, it is necessary to enlarge the area of the die only for obtaining a gain variable range of merely 40 dB.
(2) The larger the gain variable range desired to be secured is, the smaller the value of the resistor BP or BM needs to be made. Particularly, in a case where the signal to be amplified is a signal having a high frequency, AP+BP (which is equal to AM+BM for symmetry) cannot become larger than several hundreds ohms at most practically, to prevent the Miller effect. In turn, this means the resistance value of BP and BM needs to be less than several ohms, to secure 40 dB gain variable range at high frequency with the structure of FIG. 12. The amount of negative feedback which can be obtained from such a small feedback load resistance is substantially restricted, and in a typical case where the output impedance of the source of input signal is about 50Ω, it becomes harder to simultaneously achieve satisfactory input reflection characteristic, noise FIG. characteristic, and intermodulation distortion characteristic thereby. For above reasons, practically achievable gain range for the structure of the FIG. 12 is limited under 30 or 40 dB, in high frequency regions.
FIG. 14A to FIG. 14D are graphs showing the results of simulations conducted on a variable gain differential amplifier shown in FIG. 13. The Prior Art 2 is applied to the structure of FIG. 13, likewise to the structure of FIG. 12. The transistor model employed in these simulations is the same as the transistor model used in the simulations on the structure of the Prior Art 1 described above. The upper limit of the practical operating frequency of this transistor model is about 500 MHz. The LNA (Low Noise Amplifier) core current has also the same value as that in the simulations on the structure of the Prior Art 1.
FIG. 14A shows a graph plotting the changes of NF with respect to the changes of gain control voltage, regarding the cases where the frequency of an input signal input to the variable gain differential amplifier shown in FIG. 13 is 50 MHz, 275 MHz, and 500 MHz respectively. FIG. 14B shows a graph plotting the changes of S11 with respect to the changes of gain control voltage, regarding the same cases. FIG. 14C shows a graph plotting the changes of S21 with respect to the changes of gain control voltage, regarding the same cases. FIG. 14D shows a graph plotting the changes of IIP3 with respect to the changes of gain control voltage, regarding the same cases. In FIG. 14A to FIG. 14D, the plot of the case where the frequency of the input signal is 500 MHz is indicated by the boldest solid line, the plot of the case where the frequency is 275 MHz is indicated by the next boldest solid line, and the plot of the case where the frequency is 50 MHz is indicated by the thin solid line. In the simulations whose results are shown in FIG. 14A to FIG. 14D, the resistance value of the resistors r1 in FIG. 13 is set to 360Ω and the resistance value of the resistors r12 in FIG. 13 is set to 40Ω, and the gain variable range is 20 dB.
In the graphs shown in FIG. 14A to FIG. 14D, the value VAGC on the X axis indicates, in volt unit, the ½ value of the voltage at an application point 9 in the structure of FIG. 13, with respect to the electric potential of an application point 10 as a reference. Also in the structure of FIG. 13, the bases of transistors 4a and 4b are connected to the application point 9 respectively, and the bases of transistors 5a and 5b are connected to the application point 10 respectively. The gain fluctuations arising in accordance with the changes of the value VAGC are expressed by the changes of the value S21, shown in FIG. 14C. Also in the Prior Art 2, the simulations on the value IIP3 were conducted under a situation where two tone signals having frequencies which were distanced from each other by 20 kHz were input at an intensity of −50 dBm.
With reference to FIG. 14A to FIG. 14D, it is known that the results of the simulations under the settings that the frequency of the input signal is 275 MHz and 500 MHz are influenced by parasitic capacitance contained in the transistors. Accordingly, it can be considered that the simulation result of the case where the frequency of the input signal is 50 MHz is the closest to the result that can be achieved when ideal transistor elements are used.
With reference to the thin line in FIG. 14B and FIG. 14D, that is, with reference to the plot of the case where the frequency of the input signal is 50 MHz, it is known that since the amount of negative feedback is unchanged even when the gain is reduced, the values of IIP3 and S11 are nearly constant. It is further known that almost satisfactory performances are obtained for NF, S11, and IIP3, under the condition that the frequency of the input signal is 50 MHz.
On the other hand, with reference to FIG. 14D, it is known that the value of IIP3 when the gain is maximum deteriorates by about 4 dB from the value thereof when the gain is minimum, under the condition that the frequency of the input signal is 500 MHz. In order to improve the performance of IIP3 without replacing the transistors, it is necessary to make the resistance values of the resistors r1 and r12 small, mitigating the Miller effect thereby. However, in this case, there also arises a necessity of making the resistance values of resistors rfb, which constitute the negative feedback path, small, too. If the resistance values of the resistors rfb are made small, NF will deteriorate. This easiness of deterioration of the intermodulation distortion characteristic in the high frequency range is the first drawback of the structure of the Prior Art 2.
FIG. 15A to FIG. 15D are graphs showing the results of simulations conducted on the structure of FIG. 13, under the same conditions as those of FIG. 14A to FIG. 14D, except that the resistance value of the resistors r1 is set to 396Ω, the resistance value of the resistors r12 is set to 4Ω, and the gain variable range is set to 40 dB. Note that in these simulations, the resistance value of the resistors rfb in the negative feedback path is set to a small value, so that the values of S11 will be about the same values (about −16 dB) of S11 of the case where the gain variable range is 20 dB and the frequency of the input signal is 50 MHz.
Comparing the values of NF and IIP3 at the maximum gain, obtained from these simulations with the simulation results of the case where the gain variable range is 20 dB, NF deteriorates by 1 dB and IIP3 deteriorates by about 1 dBm. In order to improve the value of IIP3 to about the same value as that achieved in the case where the gain variable range is 20 dB, it is necessary to further make the resistance value of the resistors rfb small. However, this entails a further deterioration of NF. Therefore, it is difficult to increase the gain variable range to about 20 dB or greater without causing deterioration of NF and IIP3 in the structure of the Prior Art 2. This is the second drawback of the Prior Art 2.
(Other Prior Art)
Other than the above, techniques taught by Unexamined Japanese Patent Application KOKAI Publication No. 2002-252532 and Unexamined Japanese Patent Application KOKAI Publication No. 2001-7667 can be raised as the techniques for improving the variable gain amplifier circuit.
Unexamined Japanese Patent Application KOKAI Publication No. 2002-252532 discloses a method for a plurality of variable gain amplifier circuits which are connected in parallel and reduce the gain in accordance with an increase of a control voltage input from the outside, wherein the gain of the variable gain amplifier circuits is reduced when the control voltage for the variable gain amplifier circuits increases, in the order of the circuits having smaller emitter resistance values. With this method, it is considered that the noise figure characteristic and the intermodulation distortion characteristic can simultaneously be satisfied in the variable gain amplifier.
Unexamined Japanese Patent Application KOKAI Publication No. 2001-7667 discloses a method for reducing noise of a high frequency wave, by connecting a load resistor between a power source and the collector of a non-output side transistor among gain controlling transistors, and connecting a capacitor between that collector and the ground.